Benefits of attending the “High Speed Digital Design and PCB Layout” Seminars

The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have broken the 50ps barrier. This has resulted in high-speed design problems such as:

• A lack of control over impedance and reflections
• Crosstalk, bypassing, and power delivery failures
• Time delays, false triggering and reflections
• Failure to meet EMI and FCC requirements

It is the edge rate, not the frequency, which exacerbates this problem. So, even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects.

Most designs today use a microprocessor and today’s micros have clock rates about 400 times higher than the original 8 and 16 bit machines. A key factor is the minimization of the semiconductor device (now at 20 nm with the FINFETS) leading to less parasitic L and C and thereby faster switching rates. This phenomenon is also apparent in RAMs, ROMs, ASICs and Gate Arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition.

The course provides you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity.

High Speed Digital Design and PCB Layout Theory and Application

Course Outline – 3 day

This course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB.

Fundamentals

Frequency, Time and Distance
Lumped Versus Distributed Systems
Four Kinds of Reactance
Ordinary and Mutual Capacitance & Inductance
EM Fields
Geometry, C, L, & Z_o, interrelationships
C & L Resonance

BGA: Mr. Hanson discusses how to route at CAE/CAD so that the balls can be paralleled to minimize L. The pads are NSMD and 8 mils vias are on stringers. If done right, this is a very good high-speed device.

High-Speed Properties of Logic Gates

Quiescent vs. Active Dissipation
Driving Capacitive Loads
Input Power and External Power
TTL, CMOS, SiGe, In Pn, ECL, & GaAs; Output Power, Speed and engineering disciplines, dv, di effects and Voltage Margins
ICs: Cu vs Al, what are the issues?
Low K Di-electrics
Intersymbol Interference (ISI), eye diagrams and jitter
Shoot Through Current (SSO) and how to minimize it
Ground Bounce, Lead Inductance, Simultaneous Switching Noise (SSN)
Electronic Packages: QFPs, PGAs, SOIC, PLCC, BGA, COB, TAB, FC, CSP and their relationship to Signal Integrity
Lead Capacitance and Thermal Considerations

Measurement Techniques

Rise Time and Bandwidth of Oscilloscopes and probes
Self-inductance and Spurious Signal Pickup of a Probe Ground Loop
How Probes Load Down a Circuit
Special Probing Fixtures
Avoiding Pickup from Probe Shield Currents
Viewing a Serial Data Transmission System, the eye pattern closure ISI, Skin effect and tan loss.
PLL and DLLs
Slowing Down the System Clock
Observing Crosstalk
Measuring Operating Margins
Observing Metastable States in Flip-Flops

Transmission Lines

The quality factor, Q, and why lumped circuits can ring and cause EMI.
Infinite Uniform Transmission Line
Effects of Source and Load Impedance
Special Transmission Line Cases
Determining Line Impedance & Propagation Delay using TDR and VNA
Skin/proximity effect & Dielectric Loss
The Capacitive Load – Z_o and propagation delay
Matching Z₀ with trace alturations (neckdowns) – minimizing the
C load
90⁰, 45⁰ bends – are they concerns?
Characteristics of T. lines: coax, pair, micro strip, buried micro strip, stripline & differential: asymmetric, dual, edge.
Even/odd, differential/common modes are their effects on LVDS.

Terminations

End/Source/Middle Terminators
AC Biasing for End Terminators, where should it be used and how to choose the capacitor
Hairball networks, bifurcated lines and capactive stubs
Terminating differentials – Eliminating common mode and minimizing power
What causes differentials unbalance?
Diode and active terminators, Resistor Selection and Crosstalk in Terminators

Vias

Mechanical Properties of Vias
Capacitance & Inductance of Vias
Return Current and Its Relation to Vias
Through Hole, Blind, Buried, Micro Vias
Intelligent Vias and autorouters
Via discontinuity and via resonance concerns

Ground Planes and Layer Stacking

High-Speed Current Follows the Path of Least Inductance
Crosstalk in Solid and Slotted Ground Planes
Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge LVDS
Guard Traces – Do they stop crosstalk, can they resonate?
Near-End and Far-End Crosstalk
Separating analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge
Split planes – CMOS/TTL, PECL and analog using the same bias voltages
How to Stack Printed Circuit Board Layers (e.g. 4, 6, and 10 layer) for Z_o and crosstalk control, Cu fills on signal layers, minimizing warpage
Interplane Capacitance – How thin, what material and stackup placement

Power Systems

Providing a stable Voltage Reference – Cu planes
Distributing Uniform Voltage – Sense lines, bulk C and interplane C
Choosing a Bypass Capacitor – Electrolytic/tantalum and ceramic
Power plane resonance – serial and parallel, how to minimize both
Designing a .1 ohm bypass system up to F_knee
Designing for constant ESR
IC die capacitance, discrete C in the IC package
Why the 0201 and the 01005 – Both for better bypassing and EMI control
Minimizing Inductance-Capacitor layouts for SOICs, PLCCs, and various configurations of BGAs

Connectors & Cables

Mutual and Series Inductance – How Connectors Create Crosstalk
and EMI
Using Connectors on a Multidrop Bus (Z mismatch reflection) and how to match Z_c to Z_o,
Measuring Coupling in a Connector
Continuity of Gnd Underneath a Connector
Special Connectors for High-Speed requirements – Crosstalk and matching Z_o
Differential Signaling Through a Connector

PCMCIA: Mr. Hanson discusses substitution materials instead of FR4 to control capacitance. This will address its 3 mils/layer with fine lines which makes it hard to control Z0 and causes crosstalk.

Buses

Multidrop systems: Drivers, Transceivers & RAMBUS techniques
How they function, Clock rates, typical failures
ISI – Minimize the effect with Equalization and Preemphasis, DFE and CTLE
LVDS: types, unbalance, noise, layout & making them function
Methods to speed up busses – Distributive driving and load capacitance matching

Clock Distribution

Timing Margin and Clock Skew
Using Low-Impedance Drivers and Clock Distribution Lines
Source Termination of Multiple Clock Lines
Controlling Crosstalk on Clock Lines
Delay Adjustments – Serpentine traces/DACs and varisters for dynamic delay
Differential Distribution
Controlling Clock Signal Duty Cycle using the integrator
Source synchronous clocking, DDR & RDRAM

Differential Signaling

• Attributes/drawbacks of loosely/tightly coupled differential pairs
• Definition and examples of differential and common mode V and I
• Differential impedance: odd and even modes
• Advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials
• Reflections and crosstalk in differentials; metastability, Clk skew, driver skew, bit pattern sensitivity, ISI, skin effect, and dielectric constant; jitter, BER, and the eye diagram
• Matching electrical lengths

Student Materials

Each student will receive the following:

• A 326-page supplemental course notes
• Source Textbook: “High-Speed Digital Design: A Handbook of Black Magic” by Howard Johnson, PhD and Martin Graham, PhD.
• A 31-page addendum (analysis, high speed & EMI design guides)

During the course PCBs, laminates, ICs, etc. will be shown to emphasize and provide clarity to the subject being discussed.

Mr. Robert Hanson is a recognized expert: Robert Hanson, MSEE has unmatched experience in teaching and knowledge of electronics. As a Testability Overseer for Boeing Commercial Airline products, Mr. Hanson has worked with non-EEs and EE’s. He understands the need to use clear communication and he spends extra time answering student questions during his presentations or privately afterward.

Mr. Hanson has over 40 years of experience in the design manufacturing and testing areas. His initial education was in (BSIE) and Business Administration (BSBA). After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and LoraL, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implementing robotics, and participating in producibility studies and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. Mr. Hanson has extensive experience in the testing disciplines (both factory and field, commercial and military as the testability overseer for Boeing Commercial Airline products.

Building on that practical knowledge, Mr. Hanson has taught these courses many times receiving outstanding reviews each time from participants. He has presented his courses for the University of California at Berkeley, University of Wisconsin, University of Oxford (England), Seattle Pacific University, University of Washington, and most recently he teaches several classes for University of California- Los Angeles as well as for over 100 private companies on-site.

His clear instruction builds on 40 years of working experience in electronics including in manufacturing, hardware testing, and operational/test software. His teaching also reflects the fact that he has taught electronics courses throughout the United States, Europe, South Africa, the Middle East, and Asia.

Mr. Hanson has an M.S.E.E. from the University of Southern California, a B.S.E.E. from the University of Washington, and a B.S.I.E. and a B.S.B.A. from the University of North Dakota. He brings his practical experience and educational background to present a seminar that both EEs and non-EEs will find accessible and useful.

AWARDS: Boeing Company Aerospace Man of the Year for saving $6,000,000 for inventing a new testing technique for the Boeing B-1 bomber electronics.

Robert Hanson has conducted private seminars and/or consulting for 3-Com, Advanced Fibre Communications, Alcatel, Allied Signal, AMD, AMD-Dresden, Apple, AT&T, Autoliv, Boeing, Chrysler, Cisco, Compaq, Cray, da Vinci Systems, Data Device, Dell, Delphi, EDA Technologies-So. Africa, Ford, Freescale Technologies, Gateway, GE, Gen Rad, Honeywell, HP, IBM, Intel, Kaneta High Tech Materials, KLA Tencor, Lockheed, Lucent, LXE, Marconi, Micron, Motorola, NASA, NEC, eLuminant, Navico, Nortel, Northrop Grumman, Panasonic, Qualcomm, Raytheon, Rockwell, Samsung-Korea, Solectron, Storage Tek, Sun, Tektronix, Teradyne, Texas Instruments, TRW, Tyco Electronics, Tycom Laboratories, U.S. Trade Commission, United Defense, Wilson-Sonsini-Goodrich and Roseti Law Firm, Xerox, and Xilinx.

AND

ABT Media – Singapore, Autoliv, Advanced Electronic Diagnosis (AED) Saudi Arabia, Atkins Tehcnical, Inc., Bacharach, Inc., BBN Graphics, Benthos, Bourns, Compression Labs, Inc., ConMed Linvatec – California, Coulter, Dalphax, Dynalco, NASA-Edwards AFB, Hewlett Packard – Barcelona, Eldec, First Inertial Switch, Fluke, Genicom, Hathaway, Johnson & Johnson, Jet Propulsion Labs (JPL), Loral Aerospace, Martin Marietta, McBeth, Medrad, Medtronic, Motion Engineering, Inc., Norsat International, Okidata, Pharmacia Deltec, Precor, Satcom, Southern Research Institute, Wellex, Jefferson Labs, Aselsan (Turkey), Schmitt, NVE, Mc Dermott, Will, and Emery Law Firm, FLIR, Data I/O, Pulsecom, Symbol Technologies, U.S. Navy – Idaho, and JSI.

Quotes received from participants in Mr. Hanson’s course:

Fee/Registration

3 days of class $1,885.00

Discounts

$100 discount for each additional attendee from the same organization.
$100 discount for registering at least 30-days prior to the event.

Class fee includes lunch and snacks. Please contact us for any special dietary needs and/or physical accommodations.

Each student will receive the following:

• A 326-page supplemental course notes
• Source Textbook: “High-Speed Digital Design: A Handbook of Black Magic” by Howard Johnson, PhD and Martin Graham, PhD.
• A 31-page addendum (analysis, high speed & EMI design guides)