June 6-8, 2017: 8:30 am – 5:00 pm daily (3-day course)
June 9, 2017 (optional design critique)
Washington Laboratories Ltd.
7560 Lindbergh Drive
Gaithersburg, MD 20879
How to Design Printed Circuit Assemblies & Enclosures for EMI-EMC Compliance
SPECIAL BENEFIT: Daily Laboratory Tour & Demo + Day Four Optional Design Critique
This course is for three full days of instruction.
If you are a design or compliance engineer, it pays for you to know how and why EMI testing is conducted, as well as the typical causes of failure. This course offers all of the EMI information you’ll need to design compliant Printed Circuit Boards (PCBs)—including design considerations at CAE and CAD levels—for you to provide a compliant radiation/susceptibility product. You’ll examine ways to prevent common EMI/EMC problems regarding power supplies, cables, connectors, slots, discontinuity of ground planes and more. This three-day class will focus on EMI and RFI issues regarding PCBs, computers, analog designs and systems, along with relevant EMI regulations in the U.S., the European Union and Asia. Highlights include PCB radiation basics, radiation and bypass on PCBs, PCB radiation suppression techniques, grounding designs/filtering, crosstalk/termination, power and ground planes, antenna loops, spread spectrum clocking, and differential-mode and common-mode radiation. Enclosure and supplemental control techniques are presented as a part of design where the PCB control measures are restricted.
Who Should Attend
This course is directed for digital logic engineers, EMC specialists, technicians, PCB layout professionals, IC package designers, engineering managers, project managers, and others who need a working knowledge of electromagnetic compatibility engineering principles.
Frequency, time, and distance; lumped versus distributed systems, four kinds of reactance, ordinary and mutual capacitance and inductance.
EMI, source, path and receptor; threats, EMI issues, EMI regulations.
CONDUCTING A COMPLIANCE TEST WITH EMPHASIS ON THE PCB AND ENCLOSURE
Conducted emissions, radiated emissions, RF immunity, conducted RF immunity, ESD, lightening, electrical fast transient, shock and EMP.
EMI DESIGN REQUIREMENTS FOR PCBs
Interference coupling mechanism, CM radiation, antenna loops, basics of PCB radiation, PCB suppression techniques, design for immunity, switching mode power supplies (SMPS)
DESIGN CONSIDERATIONS FOR EMI COMPATIBILITY
Crosstalk – inductive/capacitive, forward/backward – how does it occur? Why does it cause radiation how is it minimized? Picket fences, Cu fills, spread spectrum clocking, bypass and radiation on PCBs, Near/Far field, differential/common coupling modes and resonance, analog circuitry.
POWER DISTRIBUTION AND GROUNDING
Power/ground planes why do they cause radiation and how is it minimized? Splits, slots, moats, floats, drawbridge, how to design for minimizing emissions from power/ground planes. How to design for digital/analog (multibias) and single bias PCBs. Ideal stackups to be EMC.
CABLES/CONNECTORS AND PCB, CONCERNS OF PCBs INTERFACING WITH FILTERING AND SHIELDING
Capacitive and magnetic shielding, slots in PCBs, shield grounding, cable radiation, shielding types, transfer impedance, shielding connection.
ENCLOSURES, MOTHERBOARDS, BACKPLANES AND BLADES
Loss of PCB ground plane in cables, how to design a PCB land trace to a connector pin to eliminate reflections, cables configuration, antenna loops with cable connections, high-speed connectors.
FILTERING AND SHIELDING
Shielding versus filtering, using ferrites, filtering mains supply, using transients suppressors on mains and I/O lines, radiation through shields.
BACKPLANE LAYOUT CONCERNS
Effects of source and load impedance and why mismatches cause radiation, the capacitive load: Zo and propagation delay and radiation effects, 90o, 45o bends, guard traces, interplane capacitance, via discontinuity and vias resonance concerns, backdrilling vias.
BUSSES AND DIFFERENTIALS
Multidrop systems, drivers, transceivers, and designing a high-speed bus, attributes/drawbacks of loosely/tightly couple differential pairs, differential impedance, advantages and disadvantages of edge (side by side), broadside (dual), asymmetric, and microstrip differentials; reflections and crosstalk in differentials, matching electrical lengths.
HIGH SPEED CLOCKING
Clock, skew and jitter, the effects of ISI, skin, and dielectric losses; the effect of various base materials of long-haul transmission, a real-world example of compensation techniques.
APERTURES, WAVE LENGTHS, ABSORPTION MATERIALS AND HEAT SINKING
The major concern today is the aperture openings versus the frequency of signals versus the higher density packaging, i.e. ICs are running hotter and the ever increasing signal edge rate. This leads to more radiation through the apertures, i.e. lamda is shorter, but more heat is generated because Power = C times F times V2.
What’s new in enclosure absorption materials and what are their capabilities for minimizing radiation? What’s new in heat sink materials (backplanes, blades, servers) which in turn alleviate the need for heat conduction through the apertures? These current issues will also be covered in the course.
Each student will be provided with a copy of “EMC for Product Designers” by Tim Williams, and comprehensive course notes. A 26-page “How to Become a Circuit Master,” a booklet which provides a detailed description of how a bareboard is manufactured and tested. In addition a 24-page addendum reinforcing information in the course notes is included and an additional 12-page addendum on laminate choices for obtaining 32-Gbit data transmission.
Demos will include a tour discussing specific test configurations:
June 6 – radiated and conducted emissions using our Open Area Test Site (OATS)
June 7 – Conducted RF immunity and ESD
June 8 – Voltage surge and magnetic field immunity.
Demos will follow the day’s lecture and begin 4 to 4:30 p.m. and will be approximately one hour.
Optional 4th Day June 9 – Critique of student designs
Mr. Hanson will review the students’ design data (PCB Layout, enclosure, schematic, etc.) and make suggestions for a more EMI-compatible design. $150 an hour (not per person i.e. if multiple persons with same company, they all can come under hourly charge). Mr. Hanson states that usually one to two hours is sufficient for the review. This time should be reserved in advance and when registering for the class. Hourly reviews will begin at 8 a.m. and last review at 2 p.m. Please request your time slot in advance. NOTE: Should you wish a critique but cannot stay for the June 9 scheduling, Mr. Hanson will do his best to schedule you (prior to June 9) in the evening at the same $150 an hour.
Robert Hanson, MSEE
Robert Hanson, MSEE has unmatched experience in teaching and knowledge of electronics. As a Testability Overseer for Boeing Commercial Airline products, Mr. Hanson has worked with non-EEs and EE’s. He understands the need to use clear communication and he spends extra time answering student questions during his presentations or privately afterward.
Mr. Hanson has over 40 years of experience in the design manufacturing and testing areas. His initial education was in (BSIE) and Business Administration (BSBA). After receiving his BSEE/MSEE, he became highly involved in all aspects of electronic testing. As a digital design engineer at The Boeing Company, Rockwell, Honeywell, and LoraL, Mr. Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs for AWACS, B1-B, 747-400, missiles, and ground support test equipment. He has played a very active role in automating the line, implementing robotics, and participating in producibility studies and working in the CAE/CAD/CAT, JIT, simulation, and automatic assembly environments. He also has performed studies and headed research projects in the computer-integrated manufacturing environment. continue
Price for 3-day course is $1,295 with a $100 discount for each addition attendee from the same organization.
Price for the 4th day is $150/hour that can be purchased in 1-hour increments.
Lunch will be provided.