The
Rohde & Schwarz customized 1,000sqft seminar facility, fully
equipped with the latest teaching tools and test equipment,
provides a state-of-the-art learning environment.
IEEE EMC Society Newsletter
Wind Turbine technology is becoming the norm as more countries install wind-generating capacity to sate the rising energy demands and, maybe, mitigate rising sea levels.
Grounding the Statue of Liberty In the Sept. issue of In Compliance magazine, our own Mike Violette talks about the challenges involved when he (and father Norm) studied Lady Liberty and helped keep a million volts out of her torch.
To commemorate our 20th anniversary, we've compiled a history of how we started and who keeps us going. We thought it was entertaining and hope you will too.
IN MEMORIAM
Dr. Joseph L.N. Violette August 24, 1932
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January 2, 2008
The speed of today’s logic devices mandates that
the interconnects on PCBs must meet the high switching rise/fall
times of these devices. Switching edges are in the 200ps to
300ps range and some devices have edges that have reached the
17ps rate. This has resulted in high-speed design problems, such
as:
• A lack of control over impedance and
reflections
• Crosstalk and bypassing failures
• Time delays, false triggering, and
reflections
• Failure to meet EMI and FCC requirements
It is the edge rate, not the frequency, that
exacerbates this problem, so even if your design is for moderate
frequency, the edge rates can cause these designs to reflect the
high-speed effects.
Most designs today use a microprocessor
and today’s micros have clock rates over 1000 times higher than
the original 8- and 16-bit machines. A key factor is the
minimization of the semiconductor device (now at 32 nm) leading
to less parasitic L and C, and thereby faster switching rates.
This phenomenon also is apparent in RAMs, ROMs, ASICs, and gate
arrays. This leads to PCBs requiring terminators, new CAD
routing disciplines, and component additions to minimize ground
bounce effects. More and more designs are requiring these faster
devices to meet more demanding specifications that match or beat
the competition.
The following one-day courses are offered to
cover the various aspects of high-speed digital design and
EMI/EMC issues :
DAY 1. Transmission Lines (T.L.) DAY 2. Crosstalk, Layer Stacking, Separating Analog/Digital
Planes, and Terminations DAY 3. Bypassing, Power Delivery, Vias, Connectors, and Buses DAY 4. Differential Signaling and Clock Distribution Control DAY 5. Key Issues for EMI/EMC: How to Design and Build a
Compliant System
These courses provide
participants with the tools for recognizing the problems with
any proposed high-speed design. Design rules and design
processes are taught that insure the PCB will function properly
at the prototype stage. Emphasis is placed on cost-competitive
design without sacrificing high-speed integrity.
The courses
are intended for digital design engineers, design managers, test
engineers, EMI/EMC engineers, IC digital logic designers,
project managers of high-speed designs, communication engineers,
and military digital engineers. No advanced math is required,
although participants will find it helpful to bring a scientific
calculator to the course. The material is presented at a
technical level that provides experienced designers with
information to design and lay out a high-speed PCB that meets
signal integrity (SI) and EMI.
Each course may be taken on a
stand-alone basis or combined as needed. While each subsequent
course builds upon the previous instruction, participants may
enroll in any course or combination.
Instruction by: Robert Hanson, MSEE
Robert Hanson has unmatched experience in teaching and
knowledge of electronics. As a Testability Overseer for
Boeing Commercial Airline products, Mr. Hanson has worked
with non-EEs and EE’s. He understands the need to use clear
communication and he spends extra time answering student
questions during his presentations or privately afterward.
Mr. Hanson has over 40 years of experience in the design
manufacturing and testing areas. His initial education was
in (BSIE) and Business Administration (BSBA). After
receiving his BSEE/MSEE, he became highly involved in all
aspects of electronic testing. Read more
Course Outline:
The following one-day courses are offered to cover the various
aspects of high-speed digital design and EMI/EMC issues:
DAY 1. Transmission Lines (T.L.) DAY 2. Crosstalk, Layer Stacking, Separating Analog/Digital
Planes, and Terminations DAY 3. Bypassing, Power Delivery, Vias, Connectors, and Buses DAY 4. Differential Signaling and Clock Distribution Control DAY 5. Key Issues for EMI/EMC: How to Design and Build a
Compliant System
Each course may be taken on a
stand-alone basis or combined as needed. While each subsequent
course builds upon the previous instruction, participants may
enroll in any course or combination.
Courses:
DAY 1. Transmission Lines (T.L.) DAY 2. Crosstalk, Layer Stacking, Separating Analog/Digital
Planes, and Terminations DAY 3. Bypassing, Power Delivery, Vias, Connectors, and Buses DAY 4. Differential Signaling and Clock Distribution Control DAY 5. Key Issues for EMI/EMC: How to Design and Build a
Compliant System
Fee/Registration:
Each course may be taken on a
stand-alone basis or combined as needed. While each subsequent
course builds upon the previous instruction, participants may
enroll in any course or combination.
1 day
2 days
3 days
4 days
5 days
$695.00
$1,340.00
$1,935.00
$2,480.00
$2,980.00
Second registrant from same organization:
receive a 10% discount
Third registrant from same organization: receive a 15% discount
This course is offered on a first-come, first-served basis.
Class sizes are limited.
Class fee includes continental-style breakfast, lunch and
afternoon breaks. Please contact us for any special dietary
needs and/or physical accommodations.
